..Solutions to ASIC and FPGA Design

SERVICES

All Trademarks Acknowledged.

Skytec Consultants Ltd 2012. All Rights Reserved.

Full FPGA/ASIC Development Life Cycle

 Research and Evaluation

 Specification

 Architecting

 Planning

 Sizing

 Pinning

 Power Estimation

 HDL Design

 RTL

 Core Integration

 DFT

 Schematic Capture

 Simulation

 Code Coverage

 Synthesis

 Place and Route

 Floor Planning

 Timing Closure

 Hardware Test

 Debug

 Characterisation

 Flow Automation

 Scripting

 Technical Documentation

 Patent Protection

Expertise

 Languages

 VHDL

 Verilog

 System Verilog

 Tcl

 Perl

 FPGA Technologies

 Altera Stratix IV GT/GX/II/I, Apex, Flex

 Xilinx Virtex II Pro/I EM, I, Spartan, 4000 Series

 Tools

 Altera Quartus II, QSYS, Signal Tap, Legacy (SOPC, Maxplus II, Classic Timing Analyser)

 Xilinx ISE, XST, Legacy

 Mentor Model/QuestaSim, Quicksim II, Leonardo, Autologic II, System Architect

 Synopsis Synplify

 Platforms

 Windows (7, Vista, XP, 2k)

 Linux (Redhat, Gnome)

 Unix (SunOS, Solaris)

Expertise

 Telecomms

 Protocols

 Ethernet (10/100/1G/10G LAN/WAN/40G)

 SONET (oc3, 12, 48, 192c)

 SDH (STM-1, 4, 16, 64)

 ATM (AAL0, 1, 2, 3/4, 5)

 Interfaces

 MII, GMII, RGMII, SGMII, XAUI, XLAUI

 SPI

 XFI/SFI

 MDI

 MDIO

 Products

 Protocol Analysers (Ethernet, SONET/SDH, ATM)

 Network Probe

 Video

 Standards

 Digital Uncompressed

 MPEG2

 MPEG Transport Stream

 Protocols

 SDI

 HD-SDI

 ltera Quartus II, QSYS, Signal Tap, Legacy (SOPC, Maxplus II, Classic Timing Analyser)

 Xilinx ISE, XST, Legacy

 Mentor Model/QuestaSim, Quicksim II, Leonardo, Autologic II, System Architect

 Synopsis Synplify

 Platforms

 Windows (7, Vista, XP, 2k)

 Linux (Redhat, Gnome)

 Unix (SunOS, Solaris)